Marc BELLEVILLE

Title of the Talk: Evolutions of the Microelectronics Technologies: a designer perspective

Abstract: Since the beginning of the Microelectronics history, scaling has always been favourable to designers: larger complexity, lower power, higher performances and lower cost. With the event of nanoscale technologies this rule is not as obvious as before. Several physical limitations are affecting transistors, reducing the design domain. Leakage is exponentially increasing, with new phenomenon like tunnel currents appearing; designer has also to handle large variability impacting devices as well as interconnects. To face those limitations, progress is expected from the technology as well as from the design and CAD tools. SOI technologies are moving towards multigate devices to provide a better electrostatic control of the channel. Metal gates and High K dielectrics are expected to drastically lower the gate leakage currents. Transistor mobility is improved by strained Si or compound semiconductors. On the design side, power and leakage mastering requires several new techniques to be used simultaneously: Voltage and Frequency scaling, power gating ... Variability implies new approaches based on statistical analysis. Multigate devices are setting new challenges and opportunities at the cell level design. Finally many advanced researches are conducted in the "Beyond CMOS area". Where, when and which of those new devices will be used is still an open issue.